ChanServ changed the topic of #armlinux to: ARM kernel talk [Upstream kernel, find your vendor forums for questions about their kernels] | https://libera.irclog.whitequark.org/armlinux
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<hanetzer> huh. that's interesting. learned something I didn't know about the kbuild system today. for every CONFIG_$FOO enabled, there appears to be a file include/config/$FOO
<steev> i would have figured it would have M/Y in there
<steev> oh, is that all only Y?
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<hanetzer> steev: unsure tbh.
<hanetzer> I was just surprised to see them :P
<hanetzer> hrm.... what does one need to do to a phy driver to make it accept @ notation?
<jn> AFAICS, nothing, the subsystem should handle devicetree integration
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<jn> (looking at phy/smsc.c)
<hanetzer> the drivers/phy/hisilicon/phy-hix5hd2-sata.c driver shares what *appear* to be more or less the same regs, however there's some reg definitions which are like y + 0x80 * i, and *that* implementation is hardcoded to a particular value of i
<jn> where are these definitions?
<hanetzer> jn: in the driver and the datasheets.
<hanetzer> hol up, I'll eyeball yours too :P
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<jn> ah, "0x010+nx0x80" in the DS
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<hanetzer> yeh
<hanetzer> yours seem pretty close as well.
<jn> since this phy is already declared with an address in the DT (phy@1900000), i see two ways forward:
<jn> 1. use two instances, one with reg = <0x1900000 0x80>, the other with reg = <0x1900080 0x80>
<jn> 2. make a new version of the DT binding that allows #phy-cells = <1>. then, a single PHY node will provide two PHYs. consumers in the devicetree will then specify phy = <&sata_phy 0> or phy = <&sata_phy 1>
<jn> option 1 looks easier because you don't have to break devicetree compatibility
<jn> Oh, and the @123 is more or less just for decoration. the information really comes from the reg attribute, AFAIUI
<hanetzer> ah
<hanetzer> well. the thing is following the 0xa0 (as mentioned in the driver itself, sata_phy0_ctll) is immediately followed by the same thing at 0xac :P
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<hanetzer> 0xa0-0xa8 is duplicated at 0xac-0xb4
<hanetzer> so SATA_PHYn_{CTLL,CTLH,STS}, where n is 0 or 1
<hanetzer> further, their definition of SATA_PORT_PHYCTL as 0x174 is in actuality 0x74 + n * 0x80, n being 2 here
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<jn> hmm
<jn> anyway, what is the hard-related behavior that you want to achieve?
<jn> currently, the driver seems to initialize the whole PHY block
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<hanetzer> ah. well. I'm *pretty sure* I've configured the sata clocks correctly, however, when the sata is plugged in dmesg is spammed with ata error messages every so often and the device node never pops up :)
<hanetzer> and comparing the bsp driver against the mainline one shows different n-values being used.
<hanetzer> (also compared against running in the qemu model I have setup)
<jn> hm
<jn> i'd try fixing it within the driver first, and caring about devicetree representation later
<hanetzer> tbh its a pretty handy tool :)
<hanetzer> so n-- in hax eh?
<hanetzer> suppose that would be enough to confirm it working, if nothing else.
<jn> the mainline driver doesn't even consider any n
<hanetzer> yep.
<jn> as to the devicetree binding: does the consumer (the AHCI driver) need to control different PHYs separately?
<jn> otherwise, the binding can stay as it is
<jn> (i retract my suggestion above of using multiple instances. it won't work with the register offsets used in the PHY driver)
<hanetzer> yeh. if they were all offsets of 0x80 it could :)
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<hanetzer> tbh not sure.
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<hanetzer> hrm. y'kno, could stick an additional property in the dt-binding, something like implemented-ports or the like, and iterate over that
<hanetzer> because yah, I can see, in the qemu trace log, it hits, one after the other, n=0,n=1 more or less immediately one after the other, going down a reg list
<hanetzer> so it hits 0x0144, then 0x01c4
<hanetzer> same values written.
<hanetzer> funny thing. my ds says BIT(23) is reserved and RO, but the vendor driver tries to write 0 to it, and my own experimentation with devmem and u-boot's md shows that bit is writable lol
<hanetzer> https://gist.githubusercontent.com/hanetzer/9aafdd837bde37fadcc8f61329237f18/raw/f8ea26fae26c0dfd02b96547d55594da4798833d/stdin << vendor kernel, in qemu (works on real hw too); look for the ahci: hisi_{wr,rd} lines :)
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<hanetzer> oh wait... 0x174 isn't 0x74 + 2*0x80; the port config regs start at 0x100 into the block
<jn> as an alternative to the implemented-ports property (not sure which option is better), you could match a chip-specific compatible string and decide how many ports to initialize based on that
<hanetzer> ahhh yeah, that works too.
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<hanetzer> hrm. now to find an example of how do to that properly :)
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<hanetzer> btw, this is the message spammed: ata1: SATA link down (SStatus 1 SControl 300)
<hanetzer> and hardcoding a simple loop from 0-1 in doesn't fix it :/
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<hanetzer> remind me again, but %X is capital hex yeh?
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<jn> yes
<jn> (without 0x prefix)
<hanetzer> aight then. I thought those were decimal numbers tbh. now I have know what its saying.
<hanetzer> device is detected but coms not set up, hrm.
<hanetzer> I swear this is gonna end up something stupid
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<hanetzer> drivers/phy/broadcom/phy-bcm63xx-usbh.c seems like this is a good enough example for how to set it up :)
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<ukleinek> broonie: it's a pleasure to send patches for asoc or spi or regulator. I cannot remember when I had to ping my patches in that area. 👍 and thanks.
<broonie> ukleinek: Tell that to the people who send complicated patches I have to think about and then get buried :/
* hanetzer cries in bsp
<hanetzer> gettin there tho :)
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