17:24 <PatD> Greetings, a question about inout pins.

17:24 <PatD> I'm integrating with a set of 3rd party verilog/ilang modules. I've created numerous wrappers using m.submodules.instance = Instance(...) without issue, but this particular one uses some inout pins, which internally, eventually get used as SB_IO PACKAGE_PINs.

17:24 <PatD> I tried many things to no avail and cannot figure out how to pass in an io_pin = ... to the Instance.

17:24 <PatD> Closest I've come comes down to

17:24 <PatD>   io_inoutpin = IOPort(1, name="my_pin")

17:24 <PatD> but it dies with cryptic errors.

17:24 <PatD> Here, "my_pin" is defined as a resource in the platform

17:24 <PatD>         Resource("my_pin", 0, Pins("19", dir="io"), Attrs(IO_STANDARD="SB_LVCMOS")),

17:24 <PatD> Not certain what else to try at this point.

17:24 <PatD> Can anyone provide a link to any examples of using Instance with bidir/inout pins or even just a complete example of IOPort usage using arbitrary pins, mapped for the platform, as above?

17:28 <whitequark[cis]> PatD: do I understand it correctly that you want to connect an FPGA pin directly to some Verilog module, which instantiates `SB_IO` itself?

17:29 <PatD> Yeah, looks that way.  Just want to pass it the raw pin, or use the equivalent of a pcf or somesuch.

17:29 <PatD> Thought I found the way with the IOPort stuff, but can't seem to grok what it wants.

17:29 <whitequark[cis]> use this: Instance("your_thing", io_whatever=platform.request("pin", dir="-").io)

17:32 <whitequark[cis]> re: cryptic errors, could you file that as a usability issue please?

17:32 <PatD> Oh!  Damn, should have pinged here sooner, stayed up way too long debugging this.  Works for one pin, will try out the whole design.

17:32 <whitequark[cis]> and I guess the overall thing is a documentation issue, since I don't think we have any place where integration with Verilog is explained

17:32 <whitequark[cis]> technically this is documented

17:32 <whitequark[cis]> but the documentation requires you to understand the whole system in depth in a way that's not really reasonable to expect

17:32 <whitequark[cis]> I mean, in order to answer this question

17:33 <PatD> Yes, I'll submit that today.  Many thanks.

17:33 <whitequark[cis]> like you could theoretically look at https://amaranth-lang.org/docs/amaranth/latest/guide.html#i-o-values and then at attributes section in https://amaranth-lang.org/docs/amaranth/latest/stdlib/io.html#amaranth.lib.io.SingleEndedPort and conclude that this is the way to go

17:33 <whitequark[cis]> but it's not good enough

17:34 <whitequark[cis]> I think for the time being we could probably just stick it into lib.io docs

17:41 <PatD> Yeah, had found my way to the first, and reviewed many times, and some parts of the second but never figured it out. The fact the .io attrib gags with "'Pin' object has no attribute 'io'." unless you have the dir="-" had me mystified.  Not certain that's anywhere in there.  In any case, will try and summarize/put the issue up.

17:41 <PatD> Seems to have solved all my issues, module works great.  Thanks again.

17:43 <whitequark[cis]> the dir="-" thing is something that's in the middle of a major deprecation/redesign cycle, which is why it's confusing

17:44 <whitequark[cis]> we're making it less confusing, but that takes a lot of time and effort

17:44 <whitequark[cis]> lib.io itself is the culmination of a major design effort we've had a few months ago that covers most of the issues, though not all

23:51 <_whitenotifier-3> [playground] purdeaandrei opened pull request #3: Fix broken link to RTLIL documentation. - https://github.com/amaranth-lang/playground/pull/3

23:58 <_whitenotifier-3> [playground] whitequark closed pull request #3: Fix broken link to RTLIL documentation. - https://github.com/amaranth-lang/playground/pull/3

23:58 <_whitenotifier-3> [amaranth-lang/playground] whitequark pushed 1 commit to main [+0/-0/±1] https://github.com/amaranth-lang/playground/compare/503df5b3cc29...2ff1cc76747b

23:58 <_whitenotifier-3> [amaranth-lang/playground] purdeaandrei 2ff1cc7 - Fix broken link to RTLIL documentation.