14:01 <sohaiber[m]> whats the main reason of having both Array and ArrayLayout? isn't slice just one comb stmt away from becoming a new Signal object?

14:14 <Wanda[cis]> Array is for multiplexing non-uniform inputs

14:14 <Wanda[cis]> * Array is useful for multiplexing non-uniform inputs

14:16 <Wanda[cis]> eg. you can implement a register interface by stuffing various registers with varying widths into an Array and reading/writing it

14:19 <sohaiber[m]> oh right i assumed fixed size elements, thanks

14:20 <Wanda[cis]> (also it predates ArrayLayout)

14:22 <Wanda[cis]> there are plans to introduce a more flexible mechanism than Array (see https://github.com/wanda-phi/rfcs/blob/choice/text/0052-choice.md), but it's most likely going to happen in 0.6

14:35 <sohaiber[m]> this is great 👍

17:51 <_whitenotifier-9> [vscode] TheZoq2 opened pull request #2: Always include all files in the project - https://github.com/YoWASP/vscode/pull/2

18:39 <Miyu-saki> Is there a way to assert reset on the test?

18:40 <whitequark[cis]> can you give more context?

18:42 <Miyu-saki> I'm looking at https://vivonomicon.com/2020/04/14/learning-fpga-design-with-nmigen/, and there's a `reset` parameter. Is there a global reset wire I can assert?

18:43 <whitequark[cis]> ah! so in simulation, all of the registers are initialized to the reset value

18:44 <whitequark[cis]> you could also do yield ResetSignal().eq(1)

18:44 <whitequark[cis]> actually hold on, that hits an issue on the latest release

18:45 <Miyu-saki> Thanks. :) And yeah, I'm encountering \> AttributeError: 'ResetSignal' object has no attribute 'reset'

18:46 <whitequark[cis]> try [this playground

18:46 <whitequark[cis]> link](https://amaranth-lang.org/play/#eyJhdiI6InYwLjQuNSIsInMiOiJmcm9tIGFtYXJhbnRoIGltcG9ydCAqXG5mcm9tIGFtYXJhbnRoLnNpbSBpbXBvcnQgU2ltdWxhdG9yLCBUaWNrXG5pbXBvcnQgYW1hcmFudGhfcGxheWdyb3VuZFxuXG5cbmVuID0gU2lnbmFsKClcbmNvdW50ID0gU2lnbmFsKDQpXG5tID0gTW9kdWxlKClcbndpdGggbS5JZihlbik6XG4gICAgbS5kLnN5bmMgKz0gY291bnQuZXEoY291bnQgKyAxKVxubS5kLmNvbWIgKz0gZW4uZXEoY291bnQgPCA1KVxuXG5tLmRvbWFpbnMuc3luYyA9IGNkX3N5bmMgPSBDbG9ja0RvbWFpbigpXG5cbl

18:46 <whitequark[cis]> xuZGVmIHRlc3RiZW5jaCgpOlxuICAgIGZvciB4IGluIHJhbmdlKDEwKTpcbiAgICAgICAgeWllbGQgY2Rfc3luYy5yc3QuZXEoeCA8IDUpXG4gICAgICAgIHlpZWxkIFRpY2soXCJzeW5jXCIpXG4gICAgICAgIHByaW50KGZcImNvdW50OiB7eWllbGQgY291bnR9XCIpXG5cbnNpbSA9IFNpbXVsYXRvcihtKVxuc2ltLmFkZF9jbG9jaygxZS02KVxuc2ltLmFkZF9wcm9jZXNzKHRlc3RiZW5jaClcbndpdGggYW1hcmFudGhfcGxheWdyb3VuZC5zaG93X3dhdmVmb3JtcyhzaW0pOlxuICAgIHNpbS5ydW4oKVxuIn0=)

18:46 <whitequark[cis]> oh wow that looks gnarly on IRC

18:47 <Miyu-saki> Yep. : P I think I can connect with Matrix

18:50 <MyrlHex[m]> Hm. Is there a limit to what gets sent to IRC? I'm curious about why this code doesn't work as I expect it to, but I'm worried about spamming IRC

18:53 <whitequark[cis]> the limit is 3 or 5 lines or something

18:53 <whitequark[cis]> but I think if you send one really massive line it doesn't get applied because Matrix

18:53 <whitequark[cis]> you could just use a paste site for this I think

18:56 <MyrlHex[m]> https://gist.github.com/adrianparvino/50cc262246011961711d2eeb57af9828#file-test-py-L67-L69

18:57 <MyrlHex[m]> Trying to understand better what clock ticks are, and I don't understand why this assertion is false.

18:58 <whitequark[cis]> ah, okay, you're hitting an awkward edge case which is going to be fixed in the next release (that'll happen in a week or two)

18:58 <whitequark[cis]> try replacing your bare yield with yield; yield Settle()

18:59 <MyrlHex[m]> Thanks. :) That works.

19:04 <whitequark[cis]> basically, yield gives you a state of the simulation just after the clock tick, and just before every combinational signal settles on their final value

19:04 <whitequark[cis]> this isn't what is wanted 98% of time, so we're fixing that (it's like this for historical reasons)

19:07 <MyrlHex[m]> Thanks! I was actually also slightly confused by the counter example's assertion, and I just thought I miscounted lol.

19:07 <whitequark[cis]> no, it's just ... weird

19:07 <whitequark[cis]> it was initially designed to be Migen-compatible but that kind of brought more pain than benefit in the end

19:13 <_whitenotifier-9> [YoWASP/vscode] whitequark pushed 1 commit to main [+0/-0/±3] https://github.com/YoWASP/vscode/compare/fca9b4ec1ca0...846964056b73

19:13 <_whitenotifier-9> [YoWASP/vscode] TheZoq2 8469640 - Provide the entire workspace folder as input to all commands.

19:16 <_whitenotifier-9> [vscode] whitequark commented on pull request #2: Always include all files in the project - https://github.com/YoWASP/vscode/pull/2#issuecomment-2127862669

19:16 <_whitenotifier-9> [vscode] whitequark closed pull request #2: Always include all files in the project - https://github.com/YoWASP/vscode/pull/2

19:16 <_whitenotifier-9> [YoWASP/vscode] whitequark tagged 8469640 as v0.3.0 https://github.com/YoWASP/vscode/commit/846964056b73981703927fbe1f7c670f30f001f6

19:16 <_whitenotifier-9> [vscode] whitequark created tag v0.3.0 - https://github.com/YoWASP/vscode

19:24 <_whitenotifier-9> [YoWASP/vscode] whitequark pushed 1 commit to main [+0/-0/±2] https://github.com/YoWASP/vscode/compare/846964056b73...61cdfc5e2af6

19:24 <_whitenotifier-9> [YoWASP/vscode] whitequark 61cdfc5 - Bump version.

19:29 <MyrlHex[m]> Hm, how do I rename the reset wire, actually? Most of my code uses reset

19:32 <MyrlHex[m]> Hey cool, I got to rewrite my Verilog code in Amaranth really quickly. :)

19:33 <MyrlHex[m]> One last question I guess: is there a way to satisfyingly do locals like this? https://gist.github.com/adrianparvino/742fccb6fd7458d4d01f8f23dfed1197#file-x-py-L55-L61

19:33 <MyrlHex[m]> `not` doesn't work.

19:33 <MyrlHex[m]> I could also just use != 1 I guess.

19:37 <whitequark[cis]> take a look at the [language guide](https://amaranth-lang.org/docs/amaranth/latest/guide.html)

19:38 <whitequark[cis]> specifically [this section](https://amaranth-lang.org/docs/amaranth/latest/guide.html#logical-operators)

19:39 <whitequark[cis]> re: the reset wire, do you mean in the output Verilog or something else?

19:39 <Miyu-saki> Yep, the Verilog output.

19:40 <whitequark[cis]> cd_sync.rst.name = "reset" is an easy one

19:40 <whitequark[cis]> you could also make it a port of your component and do m.d.comb += ResetSignal().eq(reset)

19:41 <Miyu-saki> Thanks. :) Though I'm guessing the latter technically has 2 reset inputs?

19:42 <whitequark[cis]> no, the one you're seeing now is only emitted because nothing is driving it explicitly

19:43 <whitequark[cis]> if you do verilog.convert(component) only the component ports and implicitly created clock domains cause signals to appear in the signature

19:50 <Miyu-saki> Thanks. :) I really appreciate all the help.