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KiranShila[m] >
Hey everyone! I'm getting started with amaranth and am trying to use a SyncFIFOBuffered in my design, but am a little lost on how to incorporate "standard library" blocks in an elaboratable design. Are there any examples I can check out to see how to do this?
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tpw_rules >
what do you mean? you simply import them from the library, e.g. `from nmigen.lib.fifo import SyncFIFOBuffered` then use them as you would any other amaranth module
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tpw_rules >
i copied that from an old example, that should probably be amaranth.lib.fifo :)
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KiranShila[m] >
How does one use a module?
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d1b2 >
<dragonmux> the basic pattern is: python m.submodules.name = name = SomeElaboratable() # <do stuff with name>
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tpw_rules >
yes, if you've already got elaboratable modules down that's the gist
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KiranShila[m] >
Ah, interesting. I didn't see anything about submodules in the docs other than their existence
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tpw_rules >
except instead of SomeElaboratable you use SyncFIFOBuffered of course
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KiranShila[m] >
Thanks for the link!
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KiranShila[m] >
Is there a way to get the verilog output to split each module into it's own file?
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whitequark >
not currently
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whitequark >
tbh, I'm thinking about rewriting the Verilog backend in pure Python
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whitequark >
the Yosys integration seemed like a good idea and I made it work, but I'm no longer sure it's a good idea after all
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whitequark >
the main issues are performance, and multiple file output, which is very difficult with Yosys no matter what
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