<Bluefoxicy>
Do sparse signals make sense as a language feature?
<Bluefoxicy>
Like let's say I want to do a carry-save adder adding A+B+C
<Bluefoxicy>
but B = A << 2, and C = A << 5
<Bluefoxicy>
well, the 2 LSB for the partial remainder are going to be A[1:0], the 3 LSB for the partial carry are definitely going to be 0
<tpw_rules>
isn't that something the synthesizers are already pretty smart about?
<Bluefoxicy>
yes but they also spew warnings about unused signals
<whitequark>
they are
<Bluefoxicy>
I was thinking of what happens if I sent it A being like Signal(32), B being [Signal(32), None, None] or whatnot, basically Signal(34) but I've explicitly told it the last two are not there
<Bluefoxicy>
but just a thought
<Bluefoxicy>
also yeah I've debugged code that was incorrect and I only caught it because some signals were unused and I didn't know why :|
<Bluefoxicy>
anyway right now I'm mucking about with making a multiplier, so you can imagine how that goes :D
<Bluefoxicy>
a bunch of carry-save adders dealing with inputs of different widths to make outputs of different widths
<Bluefoxicy>
docs for operations lists Repl(a, n) as "replication" but doesn't explain further I think?
<Bluefoxicy>
Repl(my_singal, 32) or Repl(32, my_signal)?
<Bluefoxicy>
I guess it's the first one assuming n is number and a is term
<whitequark>
yes
<Bluefoxicy>
s.eq( (a ^ Repl(invert_a, a_width)) & Repl(a_is_non_zero, a_width) )
<Bluefoxicy>
yeah I guess that would optimize out properly anyway
<whitequark>
minimizing combinatorial logic expressions by hand is very rarely worthwhile
<whitequark>
there are some cases, but things like this are not such
<Bluefoxicy>
Fair enough. I'm a bit overly concerned about eventual physical structure, mainly because as best I can squeeze this down, I've only gotten the multiplier's depth to be about 2 CSAs shorter than a typical wallace or dadda tree; but this is only like one or two transistors in the critical path if not perfect, if even any
<whitequark>
if you're using Yosys with abc, the netlist emitted by abc is basically unrelated to your input
<whitequark>
it'll be converted to an AIG first, then optimized, then converted to LUTs or whatever you're synthesizing to
<whitequark>
doing tricks like this is pointless if the netlist's going to become an AIG anyway
<Bluefoxicy>
atm I'm synthesizing to FPGA but, barring beating the hardware multiplier on the FPGA, it's only really useful in an ASIC design
<Bluefoxicy>
(not that I won't try to beat the hardware multiplier)
<whitequark>
I'm not really familiar with ASICs but I think usually you still use abc somewhere?
<Bluefoxicy>
I have no idea, I don't even know what tools are used for ASIC
<Bluefoxicy>
I just know FPGA has hard IP for multiplication, and soft IP is slower
<whitequark>
doing tricks like the one you're doing can pay off when the synthesis is looking for specific patterns in the input, like when it has hard carry chains that require pre-inversion
<Bluefoxicy>
I'm basically making things negative or zero before putting them in a carry-save adder
<Bluefoxicy>
that decision just happens to be in the critical path
<Bluefoxicy>
huh
<Bluefoxicy>
a mux is probably actually the optimal implementation of xor anyway
<Bluefoxicy>
bah
<Bluefoxicy>
what's the easiest way to do 3-way xnor?
<Bluefoxicy>
value = 111 or value = 000
<Bluefoxicy>
actually, that's not xnor; 3-way equality is more complicated than just xnor gate :|
<Bluefoxicy>
a.all() | (~a).all()
<Sarayan>
fpga use LUTs though, so all binary expressions with a low enough number of inputs (usually 6) are equivalent in complexity
<d1b2>
<dragonmux> correct whitequark - ABC (or ABC9) is used to perform optimisation prior to tech mapping to the standard cells of your target ASIC process
<d1b2>
<dragonmux> so it all ends up flowing through yosys' standard optimisation passes and ABC(9)
<d1b2>
<dragonmux> Bluefoxicy, if you want to learn about the open-source ASIC processes, https://openlane.readthedocs.io/en/latest/ is a good read for the OpenLANE process used by efabless/Google's Sky130 MPW
<d1b2>
<dragonmux> there are a couple of others, but that's still a good primer even for the others
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