whitequark changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/ | Bridged to #yosys:matrix.org
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<bjorkintosh> I've gotta ask my question in a different way I think.
<bjorkintosh> how do I add a constraint?
<bjorkintosh> specifically: create_clock -period 40.0 -name {i_Clk} [get_ports {i_Clk}]
<bjorkintosh> hmm.
<tpb> Title: Open Source FPGA toolchain on The Go Board [waynejohnson.net] (at blog.waynejohnson.net)
<bjorkintosh> I think I found my answer.
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