<Miyu-saki>
I know there's that Python one and that Scala(?) one and that one which looks like Rust, but I'm not too familiar with them, nor how they'd interop
<tpb>
Title: Getting started — Amaranth language & toolchain 0.5.0.dev304 documentation (at amaranth-lang.org)
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<Guest7>
what is yosys' policy on the initial values of registers with no initial value defined in verilog? (just something like "reg [10:0] foo;")
<Guest7>
from experimenting with it, it seems to assume it can be initialized to any value, usually it will be 0, unless the optimizer sees opportunities
<Guest7>
I'm targeting ECP5 and can see that it generates TRELLIS_FF elements with REGSET values depending on the verilog init value
<Guest7>
while we're at it, does anyone know how initialization/reset is supposed to work at all (with ECP5)? is there possibly an exemplary open source project using yosys that shows how it's done?
<whitequark[cis]>
Guest7: yes, 'x means the optimizer can do whatever it wants with the value
<Guest7>
nice, very simple
<Guest7>
someone somewhere claimed they were initialized by 0 by yosys, apparently that was wrong
<Guest7>
thanks, I'll check what verilog code it generates
<Guest7>
what was this about Lattice tools ignoring register init values? is that still the case? for ECP5?
<Guest7>
I saw some old posts that were sure about Lattice ignoring init values, but this could have been about ice only
<lofty>
Guest7: that's ice only, AFAIK
<lofty>
because of the different tooling used
<Guest7>
thought so
<lofty>
iCE40 registers initialise to zero
<lofty>
ECP5 registers initialise to the reset value
<lofty>
<lofty> iCE40 registers initialise to zero <-- I think this is because the SiliconBlue engineers were ex-Altera, and Altera FPGAs also initialise to zero
<Guest7>
the evil part is that the ice toolchain apparently ignores the verilog init values completely (no error or anything)
<lofty>
fortunately, we don't. though, if you ever decide to run synthesis with `-dff`, then for mapping reasons as many flops as possible will be converted to initialise to zero
<Guest7>
is there a mode that initializes registers to random values, like verilator?
<whitequark[cis]>
not explicitly but you could do it yourself
<whitequark[cis]>
setattr -set init 0 w:* or something like that in your Yosys script
<whitequark[cis]>
re: iCE40 registers, this is not visible in the toolchain
<whitequark[cis]>
Yosys adds an inverter before and after the register to simulate initializing to 1
<whitequark[cis]>
also, iCE40 isn't a Lattice FPGA; it's a SiliconBlue FPGA that was bought by Lattice
<Guest7>
yeah I read the issue where wolf added support for ice reg init like that
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