12:27 <lucaceresoli> digetx: while doing some cleanups before publishing the code for you, one question bumped on on my mind

12:28 <lucaceresoli> does the VI (and VIP input) require enabling a specific regulator?

12:29 <lucaceresoli> This is not clear from the TRM I have, and in /sys/class/regulator/ I don't see any disabled regulator that is obviously needed

12:30 <lucaceresoli> digetx: as opposed to the tegra210, where the VI driver explicitly enables avdd-dsi-csi -- but there's no regulator with that name on t20

12:34 <digetx> VI on T20 has VDDIO_VI, so yes, seems there is a regulator that needs to be enabled

13:32 <lucaceresoli> digetx: I don't find it by inspecting registers in the TRM

13:33 <lucaceresoli> can you point me to the register address, or the kernel line of code that implements it, or whatever reference for me to learn about it?

15:18 <lucaceresoli> digetx: I finished polishing a little the code and published my current work-in-progress branch

15:18 <lucaceresoli> https://github.com/lucaceresoli/linux -> tag luca/tegra20-parallel-video-capture-wip-2022-05-25

15:19 <lucaceresoli> it starts from tag v5.17, and the commits with a '****' prefix are either dirty or non-for-mainline at all

15:19 <lucaceresoli> feel free to ask any questions!

15:20 <lucaceresoli> digetx: the approach was initially to keep the existing driver structure, but as I found that the 3.1 driver I have as a reference has a completely different structure I ended up in shoehorning it into the existing driver

15:21 <lucaceresoli> my current goal is to just see something working; having a well-structured driver will come later

15:21 <lucaceresoli> digetx: thanks for you support BTW!

15:21 <digetx> okay

15:22 <digetx> the VDDIO_VI isn't documented in TRM, but you can find it in any board schematics

15:25 <lucaceresoli> digetx: unfortunately I can't: I have the board schematics but not the SoM schematics :-/

15:26 <lucaceresoli> however ican try to ask (and cross my fingers)

15:33 <lucaceresoli> but: it there any power gate inside the SoC that can prevent VI from being powered? (this actually was my initial question, I didn't think about an external one)

15:34 <digetx> there is VI power domain; but if it's powered down, then you should get a hang on accessing VI from CPU

15:36 <digetx> lucaceresoli: seems you haven't pushed branch to github

15:36 <lucaceresoli> no, it's a tag

15:36 <digetx> ah

15:36 <lucaceresoli> would you prefer a branch? I can do taht

15:37 <digetx> doesn't matter