11:03 <korken89[m]> Does anyone know if there is a Cortex-M wide limit on minimal write for the NVM controllers? I've been testing now on STM32L4 and nRF52 and both seem to support flipping an arbitrary 1 -> 0 even if other bits in the same byte are 0. Does this hold for all NOR based MCUs or are these two special?

11:03 <korken89[m]> Making algorithms that can utilize bit clearing operations is quite nice, instead of allocating a full byte.

11:04 <Lumpio-> NVM as in Flash? I would hazard a guess that the ARM spec says nothing about that

11:04 <Lumpio-> Probably entirely up to the implementor

11:23 <ithinuel[m]> From the Cortex-m perspective it doesn't matter if it's an nvm or ram etc. (The reference soc implemented on the FPGA based MPs boards mainly use ram as the code area).... (full message at <https://catircservices.org/_matrix/media/v3/download/catircservices.org/rCunATtsrYkdYhvShJcyGlBj>)

11:35 <dirbaio[m]> it's very vendor dependent

11:35 <dirbaio[m]> you have to check the docs

11:36 <dirbaio[m]> nrf52840 only allows writing each 32bit word twice.

11:37 <korken89[m]> Oh interesting, do of I try to flip 3 bits it will error

11:37 <korken89[m]> s/do/so/, s/of/if/

11:38 <korken89[m]> In 3 operations I mean

11:38 <dirbaio[m]> nrf52832 only allows 181 32bit word writes on each 512 byte block between erases 🤪

11:38 <korken89[m]> Lol

11:38 <dirbaio[m]> well, it doesn't error. I tried it and it works anyway, but it's not guaranteed to work every time

11:38 <korken89[m]> Do you know the keyword to search for in the docs?

11:39 <korken89[m]> I looked in the 52833 but could not really find anything 😅

11:39 <korken89[m]> (the one I'm testing on)

11:39 <dirbaio[m]> https://infocenter.nordicsemi.com/topic/ps_nrf52840/nvmc.html?cp=5_0_0_3_2_0#concept_ghg_zdz_vr

11:39 <dirbaio[m]> "The same 32-bit word in flash memory can only be written n WRITE number of times before a page erase must be performed."

11:40 <dirbaio[m]> seems '833 is the same

11:41 <dirbaio[m]> also there's flash with ECC, where typically you can only write each word once.

11:41 <dirbaio[m]> some STM32s have that

11:42 <korken89[m]> Interesting, thanks for the insight :D

11:42 <ithinuel[m]> dirbaio[m]: Off-topic: is infocenter a generic product ? :o

11:43 <korken89[m]> So to be safe between MCUs, one should even allocate a word per writable status you want

11:43 <dirbaio[m]> so if you want max portability, better to stick to "write only once" 🥲

11:43 <dirbaio[m]> yep

11:44 <korken89[m]> Alright, portability vs efficiency

11:44 <dirbaio[m]> also ECC words tend to be annoyingly larger. I think stm32s are 64bit (or 128bit?)

11:44 <korken89[m]> Uhoh 😅

11:44 <dirbaio[m]> so you can't even write one 32bit half now, the other 32bit half later

11:45 <korken89[m]> I think the L4i have should have that

11:45 <korken89[m]> Maybe I've not enabled ECC

11:45 <korken89[m]> I'll look is there are settings

12:27 <JamesMunns[m]> Yeah, I was wondering about this recently too. Many external SPI flash chips don't quote a limit like that, but I've been nervous writing at smaller than byte resolution (or ever multiwriting a single byte more than once)

12:30 <korken89[m]> Hehe

12:32 <fu5ha[m]> It seems setting the slew rate and drive strength of the spi data, clock, and cs pins all to fast and 8mA has solved it :D thejpster thanks for the help! Also jannic thanks for pointing me in the right direction of what to search for to actually configure that :)

12:44 <dirbaio[m]> <JamesMunns[m]> "Yeah, I was wondering about this..." <- oh yeah... the qspi flash chip I'm using (mx25something, same as in the nrf dk's)

12:44 <dirbaio[m]> * nrf dk's) doesn't quote a limit

12:44 <dirbaio[m]> but it doesn't say that multiwrite is allowed either

12:44 <dirbaio[m]> so does that mean it's not allowed? or it's allowed with no limit...??? 🤷

12:44 <JamesMunns[m]> Yeah, Ive never seen a (q)spi chip quote a limit :p

12:44 <dirbaio[m]> i'm just not doing it, just in case

12:45 <dirbaio[m]> (using it with EKV, and I made EKV not require multiwrite for portability)

12:45 <JamesMunns[m]> dirbaio[m]: Same lol, I also test that multiple writes to bytes in the same page work too :p

12:46 <JamesMunns[m]> (writes at different times, like erasing once, then writing to the same page at significantly different times, maybe even between erases of other sectors/blocks)

12:47 <JamesMunns[m]> I wonder what internal flash parts are doing differently to have limits like that :p

12:47 <korken89[m]> <dirbaio[m]> "also ECC words tend to be..." <- This was good catch, the L4 I was testing on had 64bit - and I had a if statement to check for success and a print so to test this faster i reduced logging

12:47 <korken89[m]> Just that the if statement always returned true xD

12:48 <korken89[m]> Sadness, so it means for the bootloader I need to be careful to check what it does

12:49 <korken89[m]> I should give embassy-boot a try though, extending it with signature support might be easier

12:49 <dirbaio[m]> it already has some basic support for checking ed25519 signatures

12:49 <korken89[m]> Oh

12:51 <korken89[m]> Ah yes, it's based on salty and dalek

12:52 <korken89[m]> I wonder if there is any smaller SHA512 implementation, the sha2 one takes 22kB

12:54 <korken89[m]> That's the only thing than causes me to eye P256, including SHA256 it's 12kB

12:59 <korken89[m]> <dirbaio[m]> "it already has some basic..." <- Oh it does the signature check on the firmware side, not the bootloader side