18:52 <c4017w> Anyone know a lot about synchronization between MEM-AP and MCU core accessing RAM at the same time? For example, the core write 4 consecutive bytes, 1 at a time. At the same time, the host debugger does a 32-bit read on that memory location. I imagine it's possible that I will get half old data, half new data. Is there some instruction built into

18:52 <c4017w> the ARMv7 architecture to synchronize access between the core and debugger?

19:36 <c4017w> My current solution is to have a 'data valid' flag in memory and check it before reading the rest. I think as long as the memory access order is well defined (which it does seem to be for MEM-AP), I can read out the entire data block at once and be sure that the 'data valid' flag is the first byte to actually be accessed, which will avoid any race

19:36 <c4017w> conditions