trabucayre changed the topic of #openFPGALoader to: Universal utility for programming FPGA / Github: https://github.com/trabucayre/openFPGALoader/ Logs: https://libera.irclog.whitequark.org/openFPGALoader
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<pacot24> Hello all!
<pacot24> trabucayre: I know you were working in resolving the DDR3 issues on the Tang Primer 20K and I am asking if there is some success on this.
<pacot24> On Litex of course.
<trabucayre> pacot24: not much... I don't that in my free time...
<pacot24> I am looking at the DDR modules at /litedram/modules.py but I don't see any for my hynix chip, I guess I have to create one.
<trabucayre> Module used by target is really similar
<trabucayre> I think (but maybe I'm wrong) the issue is around read (DQS module)
<pacot24> Then, I will check and compare the timings editing the default Micron module.
<pacot24> OK.
<trabucayre> Ok
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