11:01 <pivi> Hello all, I have one question on TI AM62L, it's an easy one, so maybe you can help without me having to dig too much on the topic ...

11:03 <pivi> is the architecture / boot done in a similar way as other TI K3 platform? with a cortex-R5 doing the memory init (U-Boot SPL) and than running the DM firmware and doing the handover to the cortex-A ?

11:42 <NishanthMenon> pivi Let me help confuse you as much as possible.

11:42 <NishanthMenon> Bootmaster: With the exception of AM62L, all k3 platforms have an R5F as the boot master. in AM62L A53 is the boot master.

11:42 <NishanthMenon> DM: With the exception of J721e, AM64 and AM62L, the bootmaster R5F also plays the role of Device Management (DM). in case of J721e and AM64, the security core plays both DM and security services, in the case of AM62L, TFA is supposed to play the role of DM.

11:48 <NishanthMenon> am62L is also unique in the family (in the first of what we call as k3-low now), is probably the first device without a safety implication.

11:56 <pivi> ok. got it, thanks for the explanation.

11:57 <pivi> so, the DDR RAM is configured by the SPL running on the A53, correct?

12:33 <NishanthMenon> on am62l - correct.

12:34 <NishanthMenon> there is a stub involved. vigneshr bryanb , the exact bootflow diagram - did we put something in public domain? something like what we did on u-boot for example for other k3 platforms?

12:35 <NishanthMenon> it is probably pending since linux dts is not accepted yet.. so it is probably incoming when the u-boot patches are posted, perhaps?

12:38 <pivi> NishanthMenon: I was looking for such a diagram and I was not able to find it

12:39 <NishanthMenon> pivi: yeah - i was searching as well. there are internal diagrams, but that is not something i should be throwing out ;) .. lets see if vigneshr or bryanb has something already out there.. I hope the detailed internal flow diagrams made it as part of TRM, not sure

12:56 <NishanthMenon> pivi: dhruvag2000 pointed this out: https://texasinstruments.github.io/processor-sdk-doc/processor-sdk-linux-AM62LX/esd/docs/11_00_05_02/linux/Foundational_Components/U-Boot/UG-General-Info.html#boot-flow

13:06 <bryanb> oh wow that render went bad (I'll work on that) but correct. we're using TF-A's BL1 to initialize DDR before being reset into ROM again to load tispl

13:07 <bryanb> that and link NishanthMenon mentioned BL31 is now the device manager.

13:07 <bryanb> s/link/like

13:09 <pivi> ok, so it's TF-A's BL1 configuring the DDR, not U-Boot SPL.

13:10 <pivi> so, to support different memories this component needs to be customized

13:10 <pivi> something that we are generally not doing on the other K3 SoC

13:10 <NishanthMenon> yup - part of the tradeoff to drop R5 to lower costs :(

13:17 <bryanb> yeah we tried to make it as seamless as possible (it still uses device tree config from sysconfig) but we're extremely limited on size here. 64k of sram. we had to remove just about everything we could

13:19 <pivi> well, I guess we'll play with it :-)

13:20 <pivi> bryanb: https://lore.kernel.org/all/20250408161211.3165588-1-parth105105@gmail.com/. If I remember correctly AM62 had a similar issue, just to help us you give us the exact same bugs to debug ;-)

13:21 <pivi> tomba: BTW, this ^^ was the reason of the ETH not working

13:24 <bryanb> oh gosh! I completely forgot about that. it's such a weird mux I think my scripting gets confused. good find though! I'll go back and check 62A