01:39 <jakllsch> CounterPillow: sounds like it could be timings

01:40 <CounterPillow> Yeah, I played around with the timings of the panel driver and those made a difference, but it's weird because this panel driver *should* be the right one and I shouldn't have to mess with timings

01:40 <CounterPillow> also it took me a ridiculous horizontal front porch of 1610 pixels (on a 1024 pixel active area!) to get it to line up right

01:41 <jakllsch> weird

01:41 <jakllsch> sure the FB address is right?

01:42 <CounterPillow> in the video output driver you mean? Who knows. I'd expect a different kind of scuffedness if it's wrong though.

01:43 <jakllsch> true

01:43 <CounterPillow> like a stair stepping effect rather than the whole picture shifted

01:43 <jakllsch> i know next to nothing about DSI

01:43 <jakllsch> I have this notion to write a NetBSD driver for it though at some point, if i ever find hardware

01:43 <CounterPillow> I'm gonna try the same display on my rockpro64 next to see if it's a problem with the mipi output on rk3566 or a problem with the panel

01:52 <macromorgan> CounterPillow: The PLL_VPLL clock needs to be set at something extremely close and slightly above whatever your panel's pixel clock is. Otherwise, you get the weirdness you described.

01:53 <macromorgan> if you don't provide a clock speed for it then it ends up at 24MHz I think

01:53 <CounterPillow> ! thanks

01:53 <CounterPillow> time to figure out what my panel's pixel clock is

01:58 <macromorgan> check out here where I define the PLL_VPLL clock: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353x.dtsi?h=v6.3-rc4#n20

01:58 <macromorgan> and then here where I set the pixel clock: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/gpu/drm/panel/panel-newvision-nv3051d.c?h=v6.3-rc4#n472

01:59 <macromorgan> and here's all the acceptable values for the PLL_VPLL: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/rockchip/clk-rk3568.c?h=v6.3-rc4#n26

01:59 <macromorgan> presumably if you can find the right divisors and whatnot you can add a new rate if you need it, I guess that's a question for mmind00 though.

02:02 <macromorgan> to clarify I mean extremely close to either the value or a divisible value of the pixel clock. For the RG503 which uses a different panel I set the PLL_VPLL at a straight 500MHz. That value gets me very very close to the correct pixel clock for both 50hz and 60hz modes of the panel in question though, which is good enough

02:02 <macromorgan> but the OLED panel I have doesn't run anywhere near 500MHz obviously...

02:03 <CounterPillow> Ah, thanks

02:04 <macromorgan> A dirty trick you can try is to roll back this change, then see what your parent clock is, then use that for your PLL_VPLL clock going forward: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/clk/rockchip/clk-rk3568.c?h=v6.3-rc4&id=ff3187eabb5ce478d15b6ed62eb286756adefac3

02:05 <CounterPillow> my pixel clock is 55000kHz so I should be able to use the 110lotsof0here PLL_VPLL rate

02:05 <macromorgan> yeah, give that a try and see what happens

02:06 <macromorgan> don't forget this to make sure the clock parent is PLL_VPLL: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rgxx3.dtsi?h=v6.3-rc4#n773

02:06 <macromorgan> yeah, I struggled with this quite a bit about 6-9 months ago... lol

02:07 <macromorgan> ohh, actually I remember reading a comment somewhere, forget if it was in the register descriptions or the BSP kernel but it said something about not using PLL rates above 500Mhz

02:08 <macromorgan> so maybe see if you can find a lower rate that works, though if 110+a bunch of zeroes does the trick go for it I guess

02:08 <macromorgan> want to say the restriction was for the VPLL and maybe the NPLL?

02:08 <macromorgan> mind is a blur

02:09 <macromorgan> so try it, but remember I think I saw something that said don't

02:12 <CounterPillow> wat

02:12 <CounterPillow> >[ 0.000000] clk: couldn't set vpll clk rate to 14 (-22), current rate: 24000000

02:14 <CounterPillow> oh

02:14 <CounterPillow> I'm a dummy

02:14 <CounterPillow> had a &cru before the rate :D

02:15 <CounterPillow> Yep this worked perfectly, thank you very much

06:14 <montjoie> Kwiboo: thanks

19:56 <macromorgan> is there a datasheet floating around for the rk860x regulators?