ChanServ changed the topic of #linux-rockchip to: Rockchip development discussion
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<macromorgan>
is there a way to determine what the maximum SPL stage size is for a Rockchip board? I can see in the datasheet the TPL stage (in this case a binary RAM init blob) is 64KB, but I assume the SPL max size is based on the TPL stage.
<macromorgan>
this is in reference to the rk3566
<macromorgan>
the U-Boot source from Rockchip has it as 0x10000 which is woefully inadequate, and upstream has it at 0x13800 which is still a bit small for things like GPIO and whatnot.
<macromorgan>
sorry, 0x13000
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<Kwiboo>
macromorgan: the "spl size" in mkimage refers to TPL not SPL. BootRom will read SPL to 0x0 in DRAM, and SPL will load TF-A to 0x40000 so up to 256kb should be okay for SPL
<macromorgan>
cool
<macromorgan>
for some reason mkimage is throwing a hissy fit though that my SPL is getting too big
<Kwiboo>
the SRAM size (- stack size of BootRom) is what the values in mkimage comes from, I will include an update/sync with downstream in my pending rockchip-tpl v2 series
<Kwiboo>
you should not need a very big SPL, SPL should only have feature that is needed to load FIT images and then jump to TF-A
<Kwiboo>
the SPL image is too large from mkimage should refer to the init size (tpl), and not your spl, is "ddr.bin:spl.bin" being passed to mkimage or only your spl?
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<macromorgan>
possibly... I was really really close to the limit with the 3566 and when I put in a gpio controller it went over slightly
<macromorgan>
I'm finishing up the pinctrl stuff... looks like it fixes a bug for the PX30 too
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