ChanServ changed the topic of #linux-rockchip to: Rockchip development discussion
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<macc24>
mmind00: why PLL_CPLL clock is set at 17000000 on line 216 arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts and does it also fail to set to 17000000 with -22 ending up with 24000000?
<macc24>
"clk: couldn't set cpll clk rate to 17000000 (-22), current rate: 24000000"