ChanServ changed the topic of #armlinux to: ARM kernel talk [Upstream kernel, find your vendor forums for questions about their kernels] | https://libera.irclog.whitequark.org/armlinux
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<HdkR>
Looking forward to hardware shipping with that support, should speed up my workload
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<j`ey>
HdkR: for fex or something else?
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<HdkR>
j`ey: For FEX yea
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<HdkR>
self-modifying code tracking has quite a bit of overhead
<HdkR>
Still incur the SIGSEGV overhead wrath, but nothing can be done about that
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<j`ey>
HdkR: neat. I got FEX working on the weekend. It feels a bit jittery, but I think that's probably related to the VM/GPU stuff
<HdkR>
With Asahi and Sommelier or something?
<HdkR>
I've heard that Sommelier has some frame pacing issues
<HdkR>
Apple Silicon is fun because of its hardware TSO support, because their LRCPC implementation actually just maps to the equivalent atomic accesses it isn't worth using the extension there :D
<HdkR>
(Also LRCPC isn't good enough)
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<j`ey>
HdkR: yeah asahi, but just a normal qemu VM, i think its using virtio-gpu?
<j`ey>
(so not using the 'passthrough' type stuff)
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<HdkR>
j`ey: Ah, could be anything then. Hopefully once we get code caching in place and JIT stalls will vanish
<HdkR>
in place then JIT*
<HdkR>
Always fun to see people tinkering with it
<j`ey>
I just wantes to get any setup working, once the microvm/mesa native context stuff is settled I will use that
<j`ey>
if I can persuad this person to port to arm64 or give me access to the source, that would be better.. stil working on that :)
<HdkR>
haha
<j`ey>
theres a 2nd part to this where I will havw to usw fex and wine, but I didnt tey that yet
<j`ey>
try
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<HdkR>
Wine mostly works. I think some newer version broke some path things, which I have a PR to resolve part of the problem. Only showed up with a Fedora root
<HdkR>
The ARM64ec stuff is coming along pretty well although
<maz>
j`ey: guess I'll need to invent my own hack then. write-only mappings are a thing, apparently...
<HdkR>
Hopefully we can get the CPU index in to TPIDRRO_EL0 at some point so arm64 native wine stuff can work without issue
<j`ey>
maz: good luck!
<j`ey>
HdkR: arm64ec would allow arm64 builds of wine to run x86 .exe?
<HdkR>
j`ey: Yea. ARM64 native wine which can run x86-64 executables. There's also another integration for 32-bit x86 doing the same thing
<HdkR>
Cuts out a ton of emulation time
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<j`ey>
great! right now I have to boot into macOS for this one thing
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<HdkR>
Sadly I don't have a guide to set it up, since I also don't know how to set it up. It's mostly being done by someone else on the team :D
<milkylainen>
Anyone can explain why cs_change leaves cs active after the last transaction? Also why a spidev close from userspace won't close the active cs for that device?
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<geertu>
arnd: Last time I booted lager (R-Car H1), with CONFIG_ARM_LPAE=y, was 6.8.0-something, and I got "Ignoring RAM at 0x0000000070000000-0x0000000200000000", hence much less than 1 GiB left.
<arnd>
geertu: ardb made a patch to fix qemu, so it works for me now, though I also got messages like that when sparsemem and/or highmem were turned off. If you have the .config from that boot I can try to see if I get the same on qemu now
<geertu>
If there's anything you want me to try out, please let me know. Lager is not wired up, so I don't test on that board on a regular basis.
<arnd>
thanks, let's see how far I get with my little kernel patch, that one is definitely one of the main targets I had in mind
<arnd>
geertu: is this the cortex-a9 or a15 based chip?
<geertu>
arnd: quad A15/A7 (A7 disabled)
<geertu>
config sent
<arnd>
geertu: it has CONFIG_HIGHMEM disabled and CONFIG_VMSPLIT_3G=y, so it will only see the first 800MB or so of RAM
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<geertu>
arnd: OK, that matches the behavior. What do you recommend for future testing?
<arnd>
geertu: for the moment, there is no way around using HIGHMEM if you want all of the memory to be usable, though the long-term plan is to remove that option
<arnd>
VMPLIT_1G lets you use just under 3GB of lowmem, at the expense of less userspace addressing.
<arnd>
the work that linusw__ started would let you use 4GB of physical memory and 4GB of user addressing at the expense of runtime performance
<geertu>
mvaittin: The PHY issue causing Ethernet to fail on BeagleBone Black I told you about seemed to be hone in v6.11. Until I started bisecting it, and it turns out it may happen on 6.11+, too :-(
<geertu>
arnd: Yeah, my Lager has 4 GiB.
<geertu>
s/hone/gone/
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<arnd>
geertu: I can't seem to find a reference manual for that chip, only H3 and later. This has something like 2GB of RAM in the middle of the first 4GB, and the rest above it, right?
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<geertu>
arnd: Oops, I meant R-Car H2 (not H1)
<arnd>
right, I figured that part from the core and board name
<geertu>
arnd: Yep, 1 GiB mirrored below 4 GiB, all RAM (up to 8 GiB) above 4 GiB, just like on RZ/G1H
<arnd>
I would not have guessed the mirroring bit. At least it's not as bad as TI Keystone2 where only one of the two mirrors is cache-coherent
<arnd>
geertu: With the current upstream code, this board ends up with only 1GB of lowmem then even if you use VMSPLIT_2G or VMSPLIT_1G, but if my patch works out you should be able to get up to 3GB of discontiguous lowmem
<arnd>
I'll probably ask you to do some performance testing once I can actually get it to work in qemu
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<geertu>
arnd: OK
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